1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit. More specifically, the invention relates to a semiconductor integrated circuit for performing code setting of kind identification and so forth.
2. Description of the Related Art
A conventional semiconductor circuit typically comprises ID code registers 22 to 25, a setting portion for setting codes, such as kind identification codes and so forth by multiplexers 26 to 28 and an output portion, as shown in FIG. 8. In the shown example, an identification code is expressed by 4 bits. Here, discussion will be given for the case where the identification code is "1010".
The example shown in FIG. 8, in order to avoid increasing of the ID code outputting terminals, is designed in a form of a kind of a shift register for outputting the ID code from an ID code outputting pad 29 per one bit in a serial manner.
The ID code registers 22 to 25 are constructed by D-flipflops so as to output the level of D-terminal input to Q-terminal at rising of a shift clock from a shift clock pad 21.
The multiplexers 26 to 28 output the level of A-terminal to O-terminal when the S-terminal is high level. On the other hand, the multiplexers 26 to 28 output a level of B-terminal to the O-terminal when the S-terminal is low level. Here, A-terminal is connected to a power supply line Vcc or grounding line GND depending upon the ID code of the kind.
Respective B-terminals of the multiplexers 26 to 28 are connected to Q-terminal outputs of respective ID code registers 22 to 24. Also, O-terminal outputs of respective multiplexers 26 to 28 are connected to D-terminals of respective ID code registers 23 to 25.
From the semiconductor integrated circuit, in which the setting portion for setting the code and the output portion are constructed as set forth above, ID code is output through the operation illustrated in FIG. 9. In such a case, at first, an identification code setting signal from the identification code setting signal pad 30 is turned into high level to switch the shift clock from the shift clock pad 21 into high level.
Next, the identification code setting signal from the identification code setting signal pad 30 is turned into low level to input a shift clock to the shift clock pad 21. Then, low level, high level, low level, and high level are sequentially output from an ID code outputting pad 29.
Here, if it is set to output the ID code from the ID code outputting pad 29 in the order from the least significant bit (LSB) to the most significant bit (MSB), the code "1010" can be output.
On the other hand, as shown in FIG. 10, as a semiconductor integrated circuit having built-in means for obtaining kind code of the chip in the IC chip 91 per se, there is a master slice type semiconductor integrated circuit. In this type of semiconductor integrated circuit, the identification code is set in the ROM 94 in the IC chip 91.
Here, on the IC chip 91, a function circuit portion 92 is installed. For the function circuit portion 92, a plurality of function circuit pads 99 are provided. For an address counter 93 supplying an address to ROM 94, a power source pad 95 and a counter incrementing pad 96 are provided. To the ROM 94, an output pad 97 and a grounding pad 98 are connected.
When the kind of chip is varied, the content of the ROM 94 is vat led in a wiring step in a diffusion process. When the identification code is output from the ROM 94, addresses are generated in order from the counter 93. With this address, the information read out from the ROM 94 is output to the outputting pad 97.
The above-mentioned semiconductor integrated circuit has been disclosed in detail in Japanese Unexamined Patent Publication (Kokai) No. Heisei 1-100943.
Other than the above-mentioned semiconductor integrated circuit, there is an IC chip 111 incorporating means for obtaining the kind of code of the chip per se, as illustrated in FIG. 11. In this example, nine resistors 113 having resistance of 100.OMEGA. are connected in series and ten taps 114 are extended from both ends of respective resistors 113.
In order to externally extend four taps among ten taps, bonding pads 115 to 118 are provided. It should be noted that function circuit portion 112 is installed on the IC chip 111 and a plurality of function circuit pads 119 are connected to the function circuit portion 112.
Among the bonding pads 115 to 118, the bonding pads 116 and 117 are used for establishing the identification code of the product name of the IC-chip per se. Namely, depending upon the connection of these bonding pads to the ten of taps, ID code can be differentiated.
On the other hand, as shown FIG. 12, in there is an IC chip 121 a incorporating a ROM as means for obtaining the kind code of the chip per se. In this example, in addition to a logic region 122 for performing normal signal processing and arithmetic operation, ROM region 123 is provided.
In the ROM region 123, information, such as kind name, mask name employed for fabrication of the IC and so forth written in a form of code, for setting optimal test program corresponding to a testing system when the IC chip is tested.
ROM region 123 is connected to a terminal 124 for applying a power source voltage Vcc and a terminal 125 connected to the grounding line GND similarly to the logic region 122. Also, input port 126, an output port 127, an address port 128 and a data port 129 are provided for the ROM region 123.
When the IC chip constructed as set forth above is tested, once the IC chip 121 is set in an LSI test system (not shown) as the objective IC for measurement, an information for selecting the test program written in the ROM region 123 is input to the address port 128.
When the address port 128 is accessed for inputting such information, the information stored in the ROM region 123 is read out and supplied to the LSI test system via the data bus 129. The LSI test system makes judgement for the information read out from the ROM region 123 and executes an IC test program corresponding to the read out information.
The semiconductor integrated circuit shown in FIG. 12 has been disclosed in detail in Japanese Unexamined Patent Publication (Kokai) No. Showa 62-51234.
As set forth above, in the conventional semiconductor integrated circuit, setting of the kind code is performed at the diffusion process or writing in to the ROM. Therefore, particularly in the case where the kind identification code is set in the diffusion process, it becomes impossible to set the kind identification code for the kind, such as bonding option parts whose kind name is determined only at the assembling process. Also, in writing of the identification code to the ROM by a program, it is possible that the identification code is erased by re-writing of the program.
Here, the bonding option parts are a plurality of kinds of semiconductor integrated circuit having the common basic function and only part of functions are differentiated slightly.
In such a kind of semiconductor integrated circuit, the basic function, all of the circuit for specific functions owned by each kind, a plurality of bonding pads for kind classification provided separately from the bonding pads of the terminal present in the specification of the product, and a circuit 3 for making judgement whether a plurality of bonding pads for kind classification are connected to the Vcc level or GND level, are installed on the chip.
In the above-mentioned bonding option parts, only one master pattern is diffused in the diffusion process, and the kind is determined by selectively bonding respective bonding pads to Vcc pin or GND pin corresponding to the desired kind of operation during the assembling process.
An advantage of the above-mentioned bonding option parts is that, since the master pattern in the diffusion process is only one kind, after performing all steps in the diffusion process, the kind can be determined upon assembling process depending upon demand, period for fabrication can be shortened.
However, in the conventional semiconductor integrated circuit, since the identification code is set per kinds in the diffusion process, it cannot handle setting of the identification code for the bonding option parts, the kind of which are determined upon assembling process.
Also, even in setting of the identification code for the derivative produced and so forth, for which grade of the wafer is determined by P/W (pellet/wafer) selection after the diffusion process, the conventional code setting cannot be effectively made since different identification codes have to be given per grade of the wafer during the assembling process.
Particularly, when the semiconductor integrated circuit is the bonding option parts or derivative parts or so forth, and contains a boundary scanning test circuit according to IEEE 1149.1, the foregoing problem becomes serious.
The boundary scanning test circuit is a dedicated circuit installed on the semiconductor integrated circuit for testing the board of the device. One of the tests to be performed by such boundary scanning test circuit is to make the identification code of the semiconductor device to be output.
In such the case, the ID code must correspond to the kind name on a one to one basis according to the provision under IEEE standard. Accordingly, the kind, such as the bonding option parts or derivative parts, the kinds of which are classified and determined during the assembling process, it cannot be adapted to the semiconductor integrated circuit installing the boundary scanning test circuit.